Researchers Advance Scheme to Design Seamless Integrated Circuits Etched on Graphene

University of California, Santa Barbara (UCSB) researchers say they have modeled an integrated circuit design scheme in which transistors and interconnects are monolithically patterned on a sheet of graphene. The researchers say the scheme could lead to ultra energy-efficient, flexible, and transparent electronics. Graphene-based transistors and interconnects are a nanoscale technology that could be used to solve issues with silicon-based transistors and metal interconnects. “In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns–narrow graphene ribbons can be made semiconducting while wider ribbons are metallic,” says UCSB professor Kaustav Banerjee. The researchers developed a methodology to evaluate the performance of complex circuit schemes involving many heterojunctions. “This work has demonstrated a solution for the serious contact resistance problem encountered in conventional semiconductor technology by providing an innovative idea of using an all-graphene device-interconnect scheme,” says Columbia University professor Philip Kim. The proposed all-graphene circuits have achieved 1.7 times higher noise margins and 1-2 decades lower static power consumption over current complementary metal-oxide semiconductor technology. “We hope that this work will encourage and inspire other researchers to explore graphene and beyond-graphene emerging two-dimensional crystals for designing such ‘band-gap engineered’ circuits in the near future,” Banerjee says.

More info here: UC Santa Barbara (10/22/13) Melissa Van De Werfhorst

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