A joint IBM-academic team has developed a process in which carbon nanotubes are used to randomly wire part of a chip, which is then used to generate cryptographic information, delivering an innately secure on-chip facility for hardware-based encryption. The process was developed following the team’s discovery that it is possible to produce conditions in which, on average, about 50 percent of the gates in an appropriately prepared area of the chip would be filled by nanotubes. The nanotubes are coated by a negatively-charged detergent so they become water-soluble and are channeled to a section of the chip patterned with a positively-charged substrate. Varying the spacing enables refinement of the number of locations that end up filled by a nanotube. Conditions can be established so, for example, 60 percent of the gates are occupied by a nanotube, but it is impossible to know in advance which ones will be filled. The result is a group of bits that are randomly conducting or non-conducting, from which cryptographic keys can be seeded. Moreover, combining metallic and semiconducting nanotubes enables each bit to be in one of three potential states, boosting storage density. The researchers built 64-bit test hardware and demonstrated the ability to consistently generate similar keys, suggesting it is not affected by environmental noise.
More info here: Ars Technica (02/22/16) John Timmer